[petsc-users] floating region help

[Jed Brown]

On Tue, Sep 20, 2011 at 15:26, Gong Ding <gdiso at ustc.edu> wrote:

> The problem arising from a CMOS inverter, or any CMOS gate.
> For the inverter, there are PMOS and NMOS connected together.
> When the PMOS and NMOS are both closed -- means nearly no current pass
> though the inverter.
> the connection metal will see both huge resistance at VCC and GND end.
>
>   VCC                  connection metal                      GND
>  ____    PGate        _____________________     NGate       _____
>     | ____________   |                    |  ____________  |
>   __|________________|__                __|________________|__
>    P  |           | PSource           NDrain |            | N
>   -----           -----                  -----            -----
>           NSub                                    PSub
>
> In fact, I had already add some leakage current to the inverter -- can not
> be more due to accurate limit.
> The conductance of metal still 1e6~1e10 times larger than "effective"
> conductance in the NMOS and PMOS.
>

Is this a PDE formulation or a discrete model that happens to have similar
characteristics. Semiconductor problems produce notoriously difficult
matrices for iterative methods and my understanding is that nearly all
practitioners end up using direct methods. Perhaps there is still some
exploitable structure buried in the problem, but people don't seem to have
been very successful and I don't know enough about it speculate.
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