<div class="gmail_quote">On Tue, Sep 20, 2011 at 15:26, Gong Ding <span dir="ltr"><<a href="mailto:gdiso@ustc.edu">gdiso@ustc.edu</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<div>The problem arising from a CMOS inverter, or any CMOS gate.<br>For the inverter, there are PMOS and NMOS connected together.<br>When the PMOS and NMOS are both closed -- means nearly no current pass though the inverter.<br>
the connection metal will see both huge resistance at VCC and GND end. <br> <br> VCC connection metal GND<br> ____ PGate _____________________ NGate _____<br> | ____________ | | ____________ |<br>
__|________________|__ __|________________|__ <br> P | | PSource NDrain | | N<br> ----- ----- ----- -----<br> NSub PSub<br>
<br>In fact, I had already add some leakage current to the inverter -- can not be more due to accurate limit.<br>The conductance of metal still 1e6~1e10 times larger than "effective" conductance in the NMOS and PMOS.</div>
</blockquote></div><br><div>Is this a PDE formulation or a discrete model that happens to have similar characteristics. Semiconductor problems produce notoriously difficult matrices for iterative methods and my understanding is that nearly all practitioners end up using direct methods. Perhaps there is still some exploitable structure buried in the problem, but people don't seem to have been very successful and I don't know enough about it speculate.</div>