[mpich-discuss] Hydra binding questions

[Jain, Rohit]

Okay. Let me know when you have it ready and few instructions on how to get it from trunk and use it with 1.4.

-Rohit

-----Original Message-----
From: Pavan Balaji [mailto:balaji at mcs.anl.gov] 
Sent: Tuesday, August 09, 2011 1:34 PM
To: mpich-discuss at mcs.anl.gov
Cc: Jain, Rohit
Subject: Re: [mpich-discuss] Hydra binding questions

Hi Rohit,

Just FYI, I'm working on this and hope to have it in trunk, today. 
Moving it to the 1.4.x branch will take some more time, but you can try 
out hydra from trunk if you like.

  -- Pavan

On 08/05/2011 12:38 PM, Jain, Rohit wrote:
> Pavan,
>
> I have already filed a ticket.
> Is it possible to get a patch for this fix for 1.4, so we can try and see how binding is done?
>
> -Rohit
>
> -----Original Message-----
> From: mpich-discuss-bounces at mcs.anl.gov [mailto:mpich-discuss-bounces at mcs.anl.gov] On Behalf Of Pavan Balaji
> Sent: Tuesday, August 02, 2011 9:49 AM
> To: mpich-discuss at mcs.anl.gov
> Cc: Jain, Rohit
> Subject: Re: [mpich-discuss] Hydra binding questions
>
>
> On 08/01/2011 06:38 PM, Jain, Rohit wrote:
>> 1)Is there any debug output by Hydra, which tells particular
>> core/processor binding (core numbers) associated with a process? We can
>> use this info to see variation of binding methods on different
>> architectures.
>
> Yes, good point. We don't print out the binding information in the
> verbose output currently. I'll add that in. Can you add a ticket for
> this? https://trac.mcs.anl.gov/projects/mpich2/newticket
>
>> 2)We expected cpu:sockets and cache:l3 binding to behave same on an AMD
>> box due to its layout (2 processors with 6 cores each). But, there is
>> difference in performance of about 10%. Is that expected? Again, any
>> information on binding will help, currently it is black box for us of
>> what Hydra does.
>
> Once I add print out the binding, you'll know what binding it's using.
> That might help debug this.
>
>
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-- 
Pavan Balaji
http://www.mcs.anl.gov/~balaji