<div> <br></div><blockquote style="padding-left:5px;margin-left:5px;border-left:#a0c6e5 2px solid;margin-right:0px"><br><div class="gmail_quote">On Tue, Sep 20, 2011 at 15:26, Gong Ding <span dir="ltr"><<a href="mailto:gdiso@ustc.edu">gdiso@ustc.edu</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
<div>The problem arising from a CMOS inverter, or any CMOS gate.<br>For the inverter, there are PMOS and NMOS connected together.<br>When the PMOS and NMOS are both closed -- means nearly no current pass though the inverter.<br>
the connection metal will see both huge resistance at VCC and GND end. <br> <br> VCC connection metal GND<br> ____ PGate _____________________ NGate _____<br> | ____________ | | ____________ |<br>
__|________________|__ __|________________|__ <br> P | | PSource NDrain | | N<br> ----- ----- ----- -----<br> NSub PSub<br>
<br>In fact, I had already add some leakage current to the inverter -- can not be more due to accurate limit.<br>The conductance of metal still 1e6~1e10 times larger than "effective" conductance in the NMOS and PMOS.</div>
</blockquote></div><br><div>Is this a PDE formulation or a discrete model that happens to have similar characteristics. Semiconductor problems produce notoriously difficult matrices for iterative methods and my understanding is that nearly all practitioners end up using direct methods. Perhaps there is still some exploitable structure buried in the problem, but people don't seem to have been very successful and I don't know enough about it speculate.<br><br><br>The background of this problem is the single event upset simulation of CMOS unit circuit, i.e. SRAM, latch, flip-flop.<br>They all very big, ~ 1M mesh nodes. Direct method is too slow and memory consuming. <br>Some stupid commercial code needs more than one week to simulate one particle event.<br>People usually need 100-1000 events to determine the circuit behavior! <br><br><span>Fortunately，the problem is in time domain. the transport equation of carrier has a d/dt term which helps stable.<br>The most difficult part comes from metal connection. Just use above inverter, when both NMOS and PMOS are closed, <br>the metal connection region has only displacement current from semiconductor region as eps*dE/dt, while metal region<br>the current can be written as sigma*E. The current conservation here is the boundary condition at the metal-semiconductor interface. <br>(</span><span>Since E is \frac{\partical phi}{\partical n}, here phi is the independent variable</span><span>)<br><br>Obviously, sigma >> eps/T, the governing equation of phi has a large jump parameter at the metal/semiconductor </span><span>interface</span><span>.<br>The eigen value analysis confirmed that the number of samllest eigen value equals to the number of floating metal region.<br>And the </span><span>eigen vector is exactly the floating region.</span><span> <br><br>I hope some deflation preconditioner or Neumann-</span><span>Neumann </span><span>preconditioner helps. </span><span><br>Any suggestion? <br> </span><br></div>
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